Digital phase shifting apparatus

ABSTRACT

A digital phase shifting apparatus wherein the phase of a train of sampled digital-data is changed by a fine step shorter than a sampling period using a sampling signal with a fixed phase or a clock signal, the apparatus comprising: 
     a memory unit for storing the time-axis train of sampled digital data one after another at addresses corresponding to sampling times; 
     a memory read device for reading out digital data sampled at times ahead of a current sampling time by desired time differences from the memory unit one sampled data after another in synchronization with an operation to sample the time-axis train of sampled of digital data; 
     registers for holding sampled digital data read out from the memory unit, from a most recently read data to a data ahead of the most recently read data sampled data by a predetermined piece count; and 
     an interpolated-data generating device for summing up a plurality of sampled data held in the registers with a weight applied to each of the data to generate interpolated data at a desired arbitrary point of time within sampling intervals of the sampled digital data held in the registers.

TECHNICAL FIELD

The present invention relates to a digital phase shifting apparatus. Toput it in more detail, the present invention relates to a digital phaseshifting apparatus which is capable of shifting the phase of digitaldata by a fine step shorter than the sampling period of an A/Dconverter. The digital phase shifting apparatus is implemented as delaycircuits and useful typically for an ultrasonic diagnosing apparatus.

BACKGROUND ART

An example of the conventional digital phase shifting apparatus which iscapable of shifting the phase of digital data by a fine step shorterthan the sampling period of an A/D converter is disclosed in JapanesePatent Laid-open No. 63-222745. A block diagram showing theconfiguration of an ultrasonic diagnosing apparatus disclosed inJapanese Patent Laid-open No. 63-222745 is shown in FIG. 7.

In this ultrasonic diagnosing apparatus 51, a signal received from aprobe 2 undergoes phase adjustment for all channels by a number of delaycircuits (or phase shifting circuits): a first-channel delay circuit 81to an nth-channel delay circuit 8n. The outputs of the delay circuitsare then summed up by an adder 5. The adder 5 carries out a beam formingprocess for generating a sound-ray reception signal. Based on all thesound-ray reception signals, a scan converter 6 produces pictures to bedisplayed on a display apparatus 7.

A detailed block diagram of the first-channel delay circuit 81 is shownin FIG. 8. The delay circuits of the other channels each have entirelythe same configuration. A signal received by the first-channel delaycircuit 81 is supplied to an A/D converter 82. A clock signal having apredetermined period ΔT is fed to a sampling signal delay means 83. Asynchronization signal also having the predetermined period ΔT issupplied to a synchronization means 84. The synchronization means 83delays the clock signal by a time τ1 shorter than the period ΔT,producing a sampling signal output to the A/D converter 82.

The A/D converter 82 samples the signal received by the first-channeldelay circuit 81 at sampling intervals equal to ΔT by using the samplingsignal, converting the received signal into digital data. The signalreceived by the first-channel delay circuit 81 is denoted by notations Dand D' in FIGS. 9 and 10 respectively. Digital data obtained by usingsampling signals with delay times different from each other is, on theother hand, denoted by symbols and ∘ in FIGS. 9 and 10 respectively. Fora sampling interval ΔT of 100 ns, the symbols and ∘ denote sampleddigital data for τ1 equal to 0 and 50 ns respectively.

The synchronization means 84 is used for synchronization. For example, atrain of sampled digital data denoted by the symbol ∘ lags behind atrain of sampled digital data due to the synchronization by τ1, which isshorter than the sampling period, as shown in FIG. 11. A digital delaymeans 85 is used for further delaying a signal output by thesynchronization means 84 by a delay time T1 which is equal to a multipleof the sampling interval ΔT. As a result, the first-channel delaycircuit 81 outputs digital data lagging behind the signal received bythe first channel by (τ1+T1).

A case with T1 and τ1 having values of 200 ns and 50 ns respectively isshown in FIG. 12. As a whole, the train of sampled digital data denotedby the symbol ∘ lags behind the train of sampled digital data denoted bythe symbol by a total of 250 ns.

In the conventional delay circuits 81 to 8n described above, however,sampling signals to shift the phase by amounts of time slightlydifferent from channel to channel must inevitably be used, giving riseto a problem that the control becomes complicated.

DISCLOSURE OF THE INVENTION

It is an object of the invention to provide a digital phase shiftingapparatus which is capable of changing the phase of a train of sampleddigital-data by a fine step shorter than the sampling period by means ofa sampling signal with a fixed phase or a clock signal.

A digital phase shifting apparatus provided by the present invention ischaracterized in that the digital phase shifting apparatus comprises:

a memory unit for storing a time-axis train of data sampled at fixedsampling intervals at addresses corresponding to sampling times onepiece after another;

a memory read means for reading out data sampled at times ahead of acurrent sampling time by desired time differences from the memory unitone piece after another in synchronization with an operation to samplethe time-axis train of sampled data;

registers for holding pieces of data read out from the memory unit, froma most recently read data to a data ahead of the most recently read databy a predetermined piece count; and

an interpolated-data generating means for summing up a plurality of dataheld in the registers with a weight applied to each of the data togenerate interpolated data at a desired point of time within samplingintervals of the data held in the registers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an ultrasonic diagnosing apparatus providedby the present invention;

FIG. 2 is a block diagram of an embodiment implementing a delay circuitin accordance with the present invention;

FIG. 3 is an explanatory diagram used for describing interpolated data;

FIG. 4 is an explanatory diagram used for describing a train of piecesof digital data obtained by interpolation;

FIG. 5 is an explanatory diagram used for describing a state in which adelay time shorter than a sampling interval is resulted in;

FIG. 6 is an explanatory diagram used for describing a state in which along delay time is resulted in as a whole;

FIG. 7 is an explanatory diagram used for describing the conventionalultrasonic diagnosing apparatus;

FIG. 8 is a block diagram of the conventional delay circuit;

FIG. 9 is an explanatory diagram used for describing digital dataproduced by a sampling signal without delay;

FIG. 10 is an explanatory diagram used for describing digital dataproduced by sampling signals with delays;

FIG. 11 is an explanatory diagram used for describing a state in which adelay time shorter than a sampling interval is resulted in; and

FIG. 12 is an explanatory diagram used for describing a state in which along delay time is resulted in as a whole.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will become apparent from the following detaileddescription of a preferred embodiment with reference to accompanyingdiagrams. It should be noted, however, that the range of the presentinvention is not limited to the preferred embodiment.

A block diagram of an ultrasonic diagnosing apparatus 1 employing adigital phase shifting apparatus provided by the present invention isshown in FIG. 1.

In the ultrasonic diagnosing apparatus 1, a plurality of signals(labeled "incoming signal") for n channels received by a probe 2, e.g.comprising a plurality of phased array transducer elements, are appliedthrough a bus (unnumbered) and undergo phase adjustment for theindividual channels in a number of delay circuits (or phase shiftingcircuits): a first-channel delay circuit 31 to an nth-channel delaycircuit 3n. Outputs of the delay circuits are summed up by an adder 5.The adder 5 then carries out a beam forming process to produce asound-ray signal. Based on all the sound-ray signals, a scan converter 6generates pictures to be displayed on a display unit 7.

The delay circuits 31 to 3n are provided with a common sampling signalgenerated by a sampling-signal generating circuit 4.

A detailed block diagram of the first-channel delay circuit 31 is shownin FIG. 2. The delay circuits of the other channels have exactly thesame configuration. An analog signal received by the first channel issupplied to an A/D converter 11. A sampling signal having a period ΔT isfed to the A/D converter 11, a write-control means 13 and a read-controlmeans 14.

Driven by the sampling signal, the A/D converter 11 samples the signalreceived by the first channel at sampling intervals each equal to theperiod ΔT. In FIG. 3, the analog signal received by the first channel isindicated by a notation D whereas sampled digital data is denoted by asymbol . A case with a sampling interval ΔT of 100 ns is shown in FIG.3. The sampled digital data is stored in a memory unit 12 at an addressspecified by the write-control means 13. The memory unit 12 outputs datastored at an address specified by the read-control means 14. Adifference between addresses specified by the write-control means 13 andthe read-control means 14 corresponds to a desired multiple of thesampling interval ΔT. These addresses are updated synchronously with thesampling signal.

A data register 15 is used for storing sampled digital data read outfrom the memory unit 12. Each time new sampled digital data is storedinto the data register 15, sampled digital data stored previously in thedata register 15 is shifted to a data register 16. At the same time,sampled digital data are shifted from the data register 16 to a dataregister 17, and from the data register 17 to a data register 18. Inthis way, four sampled of digital data sampled at points of timeseparated from each other by the sampling interval ΔT are stored in thedata registers 15 to 18. The four sampled data are updated by theshifting operations synchronously with the sampling signal. Theread-control means 14 controls operations to read data from the memoryunit 12 in such a way that four sampled data stored in the dataregisters 15 to 18 are ahead of the current sampling time by (T1-ΔT),T1, (T1+ΔT) and (T1+2ΔT) respectively.

Data with a fine delay time τ1 shorter than the sampling time ΔT isformed from the four sampled data typically by means of mixed splineinterpolation to be described later. Coefficient registers 19, 21, 23and 25 are each used for storing an interpolation coefficient for use inthe mixed spline interpolation. Multipliers 20, 22, 24 and 26 are usedfor multiplying the digital data stored in the data registers 15, 16, 17and 18 by the interpolation coefficients of the mixed splineinterpolation stored in the coefficient registers 19, 21, 23 and 25,respectively. The products are outputted to an adder 27 to be summed up.The operations to process such data and generate the output are carriedout synchronously with the sampling signal.

A concept of computing interpolated digital data E1 by the mixed splineinterpolation from four sampled digital data D0 to D3 stored in the dataregisters 15 to 18 respectively is shown in FIG. 3. The figure shows acase with ΔT=100 ns and τ1=50 ns.

For example, let the digital data E1 be data interpolated between thedata D1 and D2 and the distance from the data E1 to a point ofinterpolation be uΔT. According to a formula of the mixed splineinterpolation, the E1 is given by the following equation:

    E1=-(1/6)u(u-1)(u-2)D0+(1/2)(u+1)(u-1)(u-2)D1-(1/2)(u+1)u(u-2)D2+(1/6)(u+1)u(u-1)D3

It is obvious from the above equation that the interpolated data E1 is asum of the four sampled data D0 to D1 with each sampled data multipliedby a predetermined weight coefficient. The coefficients are univocallydetermined by a relative distance u from the data D1 to the point ofinterpolation. For τ1=50 ns, the relative distance u is 0.5.Coefficients for a desired point of interpolation are stored in thecoefficient registers 19, 21, 23 and 25 in advance to be used in theaddition by the adder 27 to give the desired interpolated data E1.

A signal output by the first channel is shown in FIG. 4 as a time-axisseries of pieces of digital data each denoted by a symbol □. The outputsignal of the first channel is digital data lagging behind the digitaldata stored in the data register 16 by 50 ns as shown in FIG. 5. Itshould be noted that the amount of delay τ1 is not limited to the value50 ns. The amount of delay τ1 can be determined arbitrarily by selectingthe position of the interpolation point. On the other hand, the digitaldata stored in the data register 16 was obtained at a sampling timeahead of the current sampling time by T1. As a result, the data E1 isdigital data lagging by the sum (T1+τ1). A typical case for T1=200 nsand τ1=50 ns is shown in FIG. 6. The case shown in FIG. 6 corresponds tothat of FIG. 12.

The delay circuits of the other channels each carry out the sameoperations to produce a train of sampled data lagging behind the signalinput to the channel by a desired time.

A single train of sampling pulses common to the delay circuits 31 to 3ndescribed above is used without adjusting its phase, resulting incontrol simpler than that of the conventional system. On top of that,stability of the delay time is enhanced. It should be noted that the useof the mixed spline interpolation allows calculation to be based on onlyfour points before and after an interpolation point. As a result, theinterpolation technique is suitable for a real-time system. On top ofthat, the interpolation coefficients are determined univocally for agiven delay time τ1, allowing the mixed spline interpolation to beimplemented by the same configuration as that of a transversal filterfor example. The foregoing description is illustrative of the principlesof the invention. Numerous extensions and modifications thereof would beapparent to the worker skilled in the art. All such extensions andmodifications are to be considered to be within the spirit and scope ofthe invention.

What is claimed is:
 1. A digital phase shifting apparatuscomprising:sampling signal generating means for generating samplingsignals at selected time intervals; means for sampling analog inputsignals at sampling time intervals provided by said sampling signalgenerating means and for generating a time-axis train of sampled datatherefrom; memory means for storing the time-axis train of sampled dataone after another sampled at fixed sampling intervals at addressescorresponding to sampling times; read means for reading out data sampledat times ahead of a current sampling time by desired time differencesfrom said memory means one after another in synchronization withsampling which provides said time-axis train of sampled data; aplurality of register means for holding sampled data read out from saidmemory means, said sampled data being selected from a most recently readout data to a data ahead of the most recently read out data by apredetermined data count; and interpolated data generating means forsumming up a plurality of sampled data held in said plurality ofregister means with a weighted coefficient applied to each sampled datato generate interpolated data at a desired arbitrary point in timewithin sampling intervals of the sampled data held in said plurality ofregister means, wherein said interpolated data generating meanscomprises a plurality of coefficient register means corresponding tosaid plurality of register means and for holding a predeterminedweighted coefficient, a plurality of multiplier means corresponding tosaid plurality of register means and to said plurality of coefficientregister means, and for multiplying a sampled data from thecorresponding register means with a weighted coefficient from thecorresponding coefficient register means, and an adder means for summingup outputs from said plurality of multiplier means.
 2. A digital phaseshifting apparatus according to claim 1 wherein, said interpolated datagenerating means comprises means for obtaining data at the desiredarbitrary point of time within the sampling intervals of the sampleddata held in said plurality of register means by mixed splineinterpolation.
 3. A digital phase shifting apparatus according to claim1, wherein said time-axis train of sampled data is obtained by means foranalog-to-digital conversion of a time-axis analog signal using aconstant sampling period.
 4. A digital phase shifting apparatusaccording to claim 1, wherein said plurality of coefficient registermeans weighted coefficients in said plurality of coefficient registermeans.